The present invention relates to an interface circuit for processing a signal with a small amplitude.
In recent years, the operation speeds of CPUs are increasing, and a signal of a several hundred MHz is often transferred between a CPU and a memory or a peripheral device. In a conventional logic circuit of a 0-5 V system, however, the output cannot follow up the input, or a high power is necessary for follow-up, resulting in a large amount of unnecessary noise radiation or a terminal reflected wave. To solve this problem, it is required to arrange an interface circuit called an LVTTL (Low Voltage Transistor Transistor Logic) or an SSTL (Stub Series Terminated Logic) for processing a high-speed signal with a small amplitude at the input/output portion of a device and connect it to the internal logic circuit. A signal based on the LVTTL has an amplitude of .+-.0.6 V centered on a reference voltage of 1.4 V. A signal based on the SSTL standard has an amplitude of .+-.0.2 V centered on a reference voltage of 1.5 V.
A device such as a CPU or a memory is currently often used in a battery-driven apparatus such as a portable personal computer. The battery voltage for such an apparatus is conventionally 6 V and recently lowers to 4.5 V or 3 V. Accordingly, the device is also required to operate at a low voltage and therefore must be designed to operate even when the internal power supply voltage stabilized in the device is as low as 3.3 V or 2 V.
FIG. 8 shows the arrangement of such an interface circuit (to be referred to as prior art 1 hereinafter). Referring to FIG. 8, reference symbols P1 to P4 denote p-type transistors; and N1 to N3, n-type transistors. In FIG. 8, a voltage of 3.3 V is used for a power supply Vcc. A reference voltage VREF of 1.4 V is set. The amplitude of an input signal IN to be input is VREF .+-.0.6 V.
The connection relationship in the circuit shown in FIG. 8 will be described.
The sources of the p-type transistors P1 and P3 are connected to the power supply, the gates are connected to a power down signal PD, and the drains are connected to the sources of the p-type transistors P2 and P4 constituting a current mirror, respectively. The gates of the p-type transistors P2 and P4 constituting the current mirror are connected to the drain of the transistor P2. The drain of the n-type transistor N1 is connected to the drain of the transistor P2, the gate is connected to the reference voltage, and the source is connected to the ground. The drain of the n-type transistor N2 is connected to the drain of the transistor P4 and an output terminal OUT, the gate is connected to the input terminal IN, and the source is connected to the ground. The drain of the n-type transistor N3 is connected to the output terminal OUT, the gate is connected to the power down signal PD, and the source is connected to the ground.
The operation of the circuit shown in FIG. 8 will be described next.
The transistors P1, P3, and N3 prevent this interface circuit from flowing a current in an inoperative or standby state. The control signal for these transistors is output from a CPU (not shown) or the like. When the power down signal PD goes high, the transistors P1 and P3 are turned off, and the transistor N3 is turned on. No current flows to the interface circuit, and the output OUT is set at low level. On the other hand, when the power down signal PD goes low, the transistors P1 and P3 are turned on, and the transistor N3 is turned off. A signal following up the input signal IN is output from the output OUT to access, e.g., a memory circuit (not shown). In the following description, assume that the power down signal PD is at low level, i.e., the transistors P1 and P3 are ON, and the transistor N3 is OFF unless otherwise specified.
The reference voltage VREF of, e.g., 1.4 V is input to the gate of the transistor N1, and a current corresponding to this voltage flows to the drain. The gates of the transistors P2 and P4 are connected to the drain of the transistor P2 to constitute a so-called current mirror circuit. With this arrangement, a current proportional to the drain current of the transistor N1 is output from the drain of the transistor P4.
The input signal IN is input to the gate of the transistor N2. When the input signal IN has a voltage equal to or lower than the reference voltage VREF of 1.4 V, the current drawing capability of the transistor N2 is lower than the current supply capability of the transistor P4. Therefore, the output OUT is set at high level. When the level of the received input signal IN is equal to or higher than the reference voltage VREF of 1.4 V, the current drawing capability of the transistor N2 is higher than the current supply capability of the transistor P4, so the output OUT is set at low level.
In the interface circuit shown in FIG. 8, the internal power supply voltage Vcc tends to be about 2 V to allow the operation even at a relatively low battery voltage.
In prior art 1, the transistors P1 and P2 are connected in series between the drain of the transistor N1 and the power supply. This generates a voltage drop corresponding to the sum of threshold values VT of the transistors P1 and P2, so the drain voltage of the transistor N1 is lower than the power supply voltage. On the other hand, the reference voltage VREF is set at 1.4 V based on the standard and cannot be changed. If the threshold value VT of the transistors P1 and P2 varies and exceeds 0.3 V, the drain voltage of the transistor N1 become lower than 1.4 V, and the transistor N1 does not operate. This also applies to the transistor N2.
To allow the operation in such a case while satisfying the DC characteristics of the interface circuit, the gate length (gate area) ratio of the transistor P2 to the transistor N1 and that of the transistor P4 to the transistor N2 must be increased.
However, when the gate area of the transistor P4 is increased to optimize the DC operating point, the parasitic capacitance on the drain side of the transistor N2 increases to disable the high-speed operation of the interface circuit.
This delays access from the interface circuit to the internal circuit such as a memory circuit. When a high-speed signal of 200 MHz is input as the input signal IN, the operation of the interface circuit is disabled.
Another problem is also posed.
The reference voltage of the input signal changes depending on the scheme and is set at 1 V, 1.4 V, or 1.5 V. Conventionally, interface circuits of various schema are formed in a device and switched as needed. However, the interface circuits must be arranged in units of input/output terminals. When circuits corresponding to various schema are formed in a device having a lot of input/output terminals, the chip size increases. Therefore, it is required to make an interface circuit compatible with any scheme.
To meet this requirement, in Japanese Patent Laid-Open No. 7-240679 (to be referred to as prior art 2 hereinafter), the constant current amount of a differential amplifier circuit is changed in response to a change in reference voltage, thereby preventing an increase in circuit current even when the reference voltage rises.
As another known means disclosed in Japanese Patent Laid-Open No. 5-67951 (to be referred to as prior art 3 hereinafter), the output from the interface circuit is integrated through a low-pass filter, and the integrated voltage is fed back. This arrangement allows self correction even when the DC level of the input signal or the threshold voltage of the input circuit varies.
Although prior art 2 discloses a technique of keeping current consumption constant even when the reference voltage changes, a measure against a decrease in power supply voltage is not disclosed. Generally, when the power supply voltage lowers, and the current of the constant current circuit is decreased, the gain of the differential amplifier circuit lowers, and the response time in the high-frequency characteristics is also prolonged.
In prior art 3, correction to the optimum operating point is allowed even when the reference voltage lowers. However, while the device is operating, the low-pass filter or the feedback circuit must be kept operating, resulting in an increase in power consumption.